1. Field of the Invention
This invention relates to trimming schemes for reducing the coarse DAC's nonlinearity errors in a subranging ADC to improve the ADC s spur free dynamic range.
2. Description of the Related Art
Analog-to-digital converters (ADCs) are employed to convert "real world" signals into digital signals that are susceptible to manipulation by digital computers. A subranging ADC uses a dual-pass architecture in which a buffer buffers the input voltage, a pair of resistors converts the input voltage into an input current, and a coarse quantizer quantizes the input voltage and provides a digital signal to a coarse DAC, which "reconstructs" a coarse current signal. A summing amplifier subtracts the coarse current signal from the input current to form a residual signal that is passed to a fine quantizer. The outputs of the coarse and fine quantizers are combined to form an output codeword. The subranging architecture capitalizes on the flash quantizers' speed while substantially reducing the total number of components. Subranging ADCs are discussed by Paul Horowitz, Winfield Hill, The Art of Electronics, Cambridge University Press, New York, 1989, pages 621 and 622.
The subranging ADC may exhibit significant nonlinearity errors that tend to repeat in response to an analog input signal. The repetition produces spurs in the ADC's frequency response that distort the signal and reduce its spur free dynamic range. Because the spurs tend to lie very close to the signal frequency, it is difficult and expensive to remove them using conventional filtering techniques.
Assuming a linear S/H circuit, the overall transfer function and, hence, the linearity of the subranging ADC is determined by the coarse DAC. For example, a 6-bit DAC should exhibit 20-bit accuracy in a 13-bit ADC with 20 bits of resolution whereas the fine quantizers may require only 12-bits of accuracy. The DAC's linearity is measured by the deviation of its transfer function from the ideal stair-case transfer function. The DAC's differential nonlinearity (DNL) is defined as the deviation in height between output voltages for adjacent digital codes and the value of 1 LSB. Integral nonlinearity error is the deviation of the DAC's transfer function from a straight line through the centers of the ideal stair-case transfer function and represents the accumulated DNL errors. The sources of DNL and INL errors are primarily attributable to resistor and transistor gain mismatch in the DAC.
Because the coarse DAC has limited resolution, for example 6-bits, it can be practically implemented using a unary rather than a binary topology. In an N-bit DAC, a binary topology uses only N binarily weighted current cells that are controlled by a binary codeword whereas a unary topology uses 2.sup.N -1 identical current cells that are controlled by a 2.sup.N -1 bit thermometer code. It is much easier to match the identical current cells than it is to match the binarily weighted current cells. Furthermore, the unary DAC exhibits substantially less glitch when switching. However, because the number of cells increases exponentially with the number of bits, a unary topology is rarely used in stand-alone DACs outside the subranging context. Any mismatch between the unary cells is reduced by laser trimming their bias resistors. The unary topology and laser trim improves the DAC's linearity, and thus reduces its DNL and INL errors directly.
One approach to laser trimming the DAC is to turn the cells on one at a time and trim their respective currents to a given tolerance from the ideal value. The tolerance merely creates a gain error that can be removed with a single gain adjust trim. This type of cell trim scheme can be accomplished in the context of a subranging ADC but requires external circuitry that disables the coarse quantizer and drives the DAC with a digital code that walks a 1 through each cell. Furthermore, this approach ignores and hides the code dependent errors produced by the nonlinear interaction between current cells when the DAC is operated in the context of a subranging ADC. Thus, even if each cell is trimmed perfectly the DAC will still exhibit nonlinearity errors.
Stewart S. Taylor et al. "A Dynamically Precise 50 MHz 12-Bit DAC using laser-Wafer Trimming," Proceedings of the Midwest Symposium on Circuits and Systems, pp. 1-5, 1983 describes a widely used technique for laser trimming DACs, in which a technician walks the DAC through its transfer function while trimming to the ideal cumulative value represented by the stair-case as shown in FIG. 1 of the article. This cumulative trim takes into consideration and compensates for the code dependent errors. However, because the magnitude of the signal varies over a wide dynamic range as the DAC walks up its transfer function, the test circuit cannot take full advantage of its SNR capability. Thus, the circuit's ability to resolve and thus trim the error is reduced as each addition cell is turned on. For example, in a 6-bit DAC if each unary cell ideally conducts 125 microamps with a 1 microamp tolerance, the first cell has to be trimmed to within 1 microamp with a total current of 125 microamps but the last cell has to be trimmed to within the same 1 microamp with a total current of 8 milliamps. Furthermore, the test equipment tends to exhibit its own nonlinearity over the large dynamic range. Thus, the trim compensates for test equipment's nonlinearity thereby inducing it into the DAC.